# Source Registry

## Source #1
- **Title**: ONNX Runtime Issue #24085: CUDA EP on Jetson Orin Nano does not use tensor cores
- **Link**: https://github.com/microsoft/onnxruntime/issues/24085
- **Tier**: L1 (Official GitHub issue with MSFT response)
- **Publication Date**: 2025-03-18
- **Timeliness Status**: ✅ Currently valid
- **Version Info**: ONNX Runtime v1.20.1+, JetPack 6.1, CUDA 12.6
- **Target Audience**: Jetson Orin Nano developers
- **Research Boundary Match**: ✅ Full match
- **Summary**: ONNX Runtime CUDA EP on Jetson Orin Nano is 7-8x slower than TRT standalone due to tensor cores not being utilized. Workaround: remove cudnn_conv_algo_search option and use FP16 models.
- **Related Sub-question**: Q1 (performance difference)

## Source #2
- **Title**: ONNX Runtime Issue #20457: VRAM usage difference between TRT-EP and native TRT
- **Link**: https://github.com/microsoft/onnxruntime/issues/20457
- **Tier**: L1 (Official GitHub issue with MSFT dev response)
- **Publication Date**: 2024-04-25
- **Timeliness Status**: ✅ Currently valid
- **Version Info**: ONNX Runtime 1.17.1, CUDA 12.2
- **Target Audience**: All ONNX Runtime + TRT users
- **Research Boundary Match**: ✅ Full match
- **Summary**: ONNX Runtime TRT-EP keeps serialized engine in memory (~420-440MB) during execution. Native TRT drops to 130-140MB after engine build by calling releaseBlob(). Delta: ~280-300MB.
- **Related Sub-question**: Q2 (memory overhead)

## Source #3
- **Title**: ONNX Runtime Issue #12083: TensorRT Provider vs TensorRT Native
- **Link**: https://github.com/microsoft/onnxruntime/issues/12083
- **Tier**: L2 (Official MSFT dev response)
- **Publication Date**: 2022-07-05 (confirmed still relevant)
- **Timeliness Status**: ⚠️ Needs verification (old but fundamental architecture hasn't changed)
- **Version Info**: General ONNX Runtime
- **Target Audience**: All ONNX Runtime users
- **Research Boundary Match**: ✅ Full match
- **Summary**: MSFT engineer confirms TRT-EP "can achieve performance parity with native TensorRT." Benefit is automatic fallback for unsupported ops.
- **Related Sub-question**: Q1 (performance difference)

## Source #4
- **Title**: ONNX Runtime Issue #11356: Lower performance on InceptionV3/4 with TRT EP
- **Link**: https://github.com/microsoft/onnxruntime/issues/11356
- **Tier**: L4 (Community report)
- **Publication Date**: 2022
- **Timeliness Status**: ⚠️ Needs verification
- **Version Info**: ONNX Runtime older version
- **Target Audience**: ONNX Runtime users
- **Research Boundary Match**: ⚠️ Partial (different model, but same mechanism)
- **Summary**: Reports ~3x performance difference (41 vs 129 inferences/sec) between ONNX RT TRT-EP and native TRT on InceptionV3/4.
- **Related Sub-question**: Q1 (performance difference)

## Source #5
- **Title**: NVIDIA JetPack 6.2 Release Notes
- **Link**: https://docs.nvidia.com/jetson/archives/jetpack-archived/jetpack-62/release-notes/index.html
- **Tier**: L1 (Official NVIDIA documentation)
- **Publication Date**: 2025-01
- **Timeliness Status**: ✅ Currently valid
- **Version Info**: JetPack 6.2, TensorRT 10.3, CUDA 12.6, cuDNN 9.3
- **Target Audience**: Jetson developers
- **Research Boundary Match**: ✅ Full match
- **Summary**: JetPack 6.2 includes TensorRT 10.3, enables Super Mode for Orin Nano (67 TOPS, 1020 MHz GPU, 25W).
- **Related Sub-question**: Q3 (conversion paths)

## Source #6
- **Title**: NVIDIA Jetson Orin Nano Super Developer Kit Blog
- **Link**: https://developer.nvidia.com/blog/nvidia-jetson-orin-nano-developer-kit-gets-a-super-boost/
- **Tier**: L2 (Official NVIDIA blog)
- **Publication Date**: 2025
- **Timeliness Status**: ✅ Currently valid
- **Version Info**: Orin Nano Super, 67 TOPS sparse INT8
- **Target Audience**: Jetson developers
- **Research Boundary Match**: ✅ Full match
- **Summary**: Super mode: GPU 1020 MHz (vs 635), 67 TOPS sparse (vs 40), memory bandwidth 102 GB/s (vs 68), power 25W. No DLA cores on Orin Nano.
- **Related Sub-question**: Q6 (DLA availability)

## Source #7
- **Title**: Jetson Orin module comparison (Connect Tech)
- **Link**: https://connecttech.com/jetson/jetson-module-comparison
- **Tier**: L3 (Authoritative hardware vendor)
- **Publication Date**: 2025
- **Timeliness Status**: ✅ Currently valid
- **Target Audience**: Jetson hardware buyers
- **Research Boundary Match**: ✅ Full match
- **Summary**: Confirms Orin Nano has NO DLA cores. Orin NX has 1-2 DLA. AGX Orin has 2 DLA.
- **Related Sub-question**: Q6 (DLA availability)

## Source #8
- **Title**: TensorRT Engine hardware specificity (NVIDIA/TensorRT Issue #1920)
- **Link**: https://github.com/NVIDIA/TensorRT/issues/1920
- **Tier**: L1 (Official NVIDIA TensorRT repo)
- **Publication Date**: 2022 (confirmed still valid for TRT 10)
- **Timeliness Status**: ✅ Currently valid
- **Version Info**: All TensorRT versions
- **Target Audience**: TensorRT developers
- **Research Boundary Match**: ✅ Full match
- **Summary**: TRT engines are tied to specific GPU models. Must build on target hardware. Cannot cross-compile x86→aarch64.
- **Related Sub-question**: Q4 (deployment workflow)

## Source #9
- **Title**: trtexec ONNX to TRT conversion on Jetson Orin Nano (StackOverflow)
- **Link**: https://stackoverflow.com/questions/78787534/converting-a-pytorch-onnx-model-to-tensorrt-engine-jetson-orin-nano
- **Tier**: L4 (Community)
- **Publication Date**: 2024
- **Timeliness Status**: ✅ Currently valid
- **Target Audience**: Jetson developers
- **Research Boundary Match**: ✅ Full match
- **Summary**: Standard workflow: trtexec --onnx=model.onnx --saveEngine=model.trt --fp16. Use --memPoolSize instead of deprecated --workspace.
- **Related Sub-question**: Q3, Q5 (conversion workflow)

## Source #10
- **Title**: TensorRT 10 Python API Documentation
- **Link**: https://docs.nvidia.com/deeplearning/tensorrt/10.15.1/inference-library/python-api-docs.html
- **Tier**: L1 (Official NVIDIA docs)
- **Publication Date**: 2025
- **Timeliness Status**: ✅ Currently valid
- **Version Info**: TensorRT 10.x
- **Target Audience**: TensorRT Python developers
- **Research Boundary Match**: ✅ Full match
- **Summary**: TRT 10 uses tensor-based API (not binding indices). load engine via runtime.deserialize_cuda_engine(). Async inference via context.enqueue_v3(stream_handle).
- **Related Sub-question**: Q3 (conversion paths)

## Source #11
- **Title**: Torch-TensorRT JetPack documentation
- **Link**: https://docs.pytorch.org/TensorRT/v2.10.0/getting_started/jetpack.html
- **Tier**: L1 (Official documentation)
- **Publication Date**: 2025
- **Timeliness Status**: ✅ Currently valid
- **Version Info**: Torch-TensorRT, JetPack 6.2, PyTorch 2.8.0
- **Target Audience**: PyTorch developers on Jetson
- **Research Boundary Match**: ✅ Full match
- **Summary**: Torch-TensorRT supports Jetson aarch64 with JetPack 6.2. Supports AOT compilation, FP16/INT8, dynamic shapes.
- **Related Sub-question**: Q3 (conversion paths)

## Source #12
- **Title**: XFeatTensorRT GitHub repo
- **Link**: https://github.com/PranavNedunghat/XFeatTensorRT
- **Tier**: L4 (Community)
- **Publication Date**: 2024
- **Timeliness Status**: ✅ Currently valid
- **Target Audience**: XFeat users on NVIDIA GPUs
- **Research Boundary Match**: ✅ Full match
- **Summary**: C++ TRT implementation of XFeat feature extraction. Already converts XFeat to TRT engine.
- **Related Sub-question**: Q5 (XFeat conversion)

## Source #13
- **Title**: TensorRT Best Practices (Official NVIDIA)
- **Link**: https://docs.nvidia.com/deeplearning/tensorrt/latest/performance/best-practices.html
- **Tier**: L1 (Official NVIDIA docs)
- **Publication Date**: 2025
- **Timeliness Status**: ✅ Currently valid
- **Version Info**: TensorRT 10.x
- **Target Audience**: TensorRT developers
- **Research Boundary Match**: ✅ Full match
- **Summary**: Comprehensive guide: use trtexec for benchmarking, --fp16 for FP16, use ModelOptimizer for INT8, use polygraphy for model inspection.
- **Related Sub-question**: Q3 (conversion workflow)

## Source #14
- **Title**: NVIDIA blog: Maximizing DL Performance on Jetson Orin with DLA
- **Link**: https://developer.nvidia.com/blog/maximizing-deep-learning-performance-on-nvidia-jetson-orin-with-dla/
- **Tier**: L2 (Official NVIDIA blog)
- **Publication Date**: 2024
- **Timeliness Status**: ✅ Currently valid
- **Target Audience**: Jetson Orin developers (NX and AGX)
- **Research Boundary Match**: ⚠️ Partial (DLA not available on Orin Nano)
- **Summary**: DLA contributes 38-74% of total DL performance on Orin (NX/AGX). Supports CNN layers in FP16/INT8. NOT available on Orin Nano.
- **Related Sub-question**: Q6 (DLA availability)

## Source #15
- **Title**: PUT Vision Lab: TensorRT vs ONNXRuntime comparison on Jetson
- **Link**: https://putvision.github.io/article/2021/12/20/jetson-onnxruntime-tensorrt.html
- **Tier**: L3 (Academic lab blog)
- **Publication Date**: 2021 (foundational comparison, architecture unchanged)
- **Timeliness Status**: ⚠️ Needs verification (older, but core findings still apply)
- **Target Audience**: Jetson developers
- **Research Boundary Match**: ⚠️ Partial (older Jetson, but same TRT vs ONNX RT question)
- **Summary**: Native TRT generally faster. ONNX RT TRT-EP adds wrapper overhead. Both use same TRT kernels internally.
- **Related Sub-question**: Q1 (performance difference)

## Source #16
- **Title**: LiteSAM paper — MinGRU details (Eqs 12-16, Section 3.4.2)
- **Link**: https://www.mdpi.com/2072-4292/17/19/3349
- **Tier**: L1 (Peer-reviewed paper)
- **Publication Date**: 2025
- **Timeliness Status**: ✅ Currently valid
- **Target Audience**: Satellite-aerial matching researchers
- **Research Boundary Match**: ✅ Full match
- **Summary**: MinGRU subpixel refinement uses 4 stacked layers, 3×3 window (9 candidates). Gates depend only on input C_f. Ops: Linear, Sigmoid, Mul, Add, ReLU, Tanh.
- **Related Sub-question**: Q5 (LiteSAM TRT compatibility)

## Source #17
- **Title**: Coarse_LoFTR_TRT paper — LoFTR TRT adaptation for embedded devices
- **Link**: https://ar5iv.labs.arxiv.org/html/2202.00770
- **Tier**: L2 (arXiv paper with working open-source code)
- **Publication Date**: 2022
- **Timeliness Status**: ✅ Currently valid (TRT adaptation techniques still apply)
- **Target Audience**: Feature matching on embedded devices
- **Research Boundary Match**: ✅ Full match
- **Summary**: Documents specific code changes for TRT compatibility: einsum→elementary ops, ONNX export, knowledge distillation. Tested on Jetson Nano 2GB. 2.26M params reduced from 27.95M.
- **Related Sub-question**: Q5 (EfficientLoFTR as TRT-proven alternative)

## Source #18
- **Title**: minGRU paper — "Were RNNs All We Needed?"
- **Link**: https://huggingface.co/papers/2410.01201
- **Tier**: L1 (Research paper)
- **Publication Date**: 2024-10
- **Timeliness Status**: ✅ Currently valid
- **Target Audience**: RNN/sequence model researchers
- **Research Boundary Match**: ✅ Full match
- **Summary**: MinGRU removes gate dependency on h_{t-1}, enabling parallel computation. Parallel implementation uses logcumsumexp for numerical stability. 175x faster than sequential for seq_len=512.
- **Related Sub-question**: Q5 (MinGRU TRT compatibility)

## Source #19
- **Title**: SAM2 TRT performance degradation issue
- **Link**: https://github.com/facebookresearch/sam2/issues/639
- **Tier**: L4 (GitHub issue)
- **Publication Date**: 2024
- **Timeliness Status**: ✅ Currently valid
- **Target Audience**: SAM/transformer TRT deployers
- **Research Boundary Match**: ⚠️ Partial (different model, but relevant for transformer attention TRT risks)
- **Summary**: SAM2 MemoryAttention 30ms PyTorch → 100ms TRT FP16. RoPEAttention bottleneck. Warning for transformer TRT conversion.
- **Related Sub-question**: Q7 (TRT conversion risks)

## Source #20
- **Title**: EfficientLoFTR (CVPR 2024)
- **Link**: https://github.com/zju3dv/EfficientLoFTR
- **Tier**: L1 (CVPR paper + open-source code)
- **Publication Date**: 2024
- **Timeliness Status**: ✅ Currently valid
- **Target Audience**: Feature matching researchers
- **Research Boundary Match**: ✅ Full match
- **Summary**: 2.5x faster than LoFTR, higher accuracy. 15.05M params. Semi-dense matching. Available on HuggingFace under Apache 2.0. 964 GitHub stars.
- **Related Sub-question**: Q5 (alternative satellite matcher)
