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[autodev] Step 13 partial: c1/c2/c2_5/c3 cycle-1 doc sync

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Item 2 (C1) + item 3 batch 1 of ~5 (C2 VPR, C2.5 Rerank, C3 Matcher)
of the cycle-1 component-description reconciliation called out in
ripple_log_cycle1.md.

For each touched description.md:
- Add a "Cycle-1 operational reality" paragraph in section 1 that
  names the _STRATEGY_REGISTRY + register_airborne_strategies()
  runtime gate (AZ-591), the pre_constructed dict path through
  compose_root (AZ-618 umbrella), the per-component
  AIRBORNE_REQUIRED_PRE_CONSTRUCTED_KEYS row, and any cycle-1
  strategy-default vs documented-primary disambiguation
  (net_vlad as the C2 default; xfeat parked from the C3 airborne
  registry).
- Relax the OpenCV row in section 5 Key Dependencies to the
  D-CROSS-CVE-1 cycle-1 pin (>=4.11.0.86,<4.12) wherever the
  component imports cv2 (C2 preprocessors, C2.5 ORB placeholder,
  C3 RANSAC + reprojection).
- Add a "Cycle-1 Tier-2 follow-up dependencies" subsection in
  section 7 only for components with a strategy module that is
  built but parked from the airborne registry (C3 xfeat).

Refresh ripple_log_cycle1.md follow-up ordering with per-batch
progress + extracted batch pattern so the next batch session has
a self-contained recipe. Bump _autodev_state.md sub_step.detail
to reflect batch 1 completion (10 components + 8 helpers + tests/
remain).

Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
Oleksandr Bezdieniezhnykh
2026-05-19 16:49:41 +03:00
parent 4fd88655a4
commit c1f27e4681
6 changed files with 28 additions and 8 deletions
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_docs/02_document/components/02_c2_vpr/description.md
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@@ -6,6 +6,8 @@
**Architectural Pattern**: Strategy — `VprStrategy` interface; concrete implementations (UltraVPR primary, MegaLoc secondary, MixVPR / SelaVPR / EigenPlaces / NetVLAD / SALAD additional candidates) selected at startup by config (ADR-001); build-time gated per-implementation by `BUILD_*` flags (ADR-002); composition-root wired (ADR-009).
**Cycle-1 operational reality**: the airborne binary wires C2 through the `_STRATEGY_REGISTRY` + `register_airborne_strategies()` runtime gate (AZ-591) on top of the build-flag matrix, and constructor injection flows through the `pre_constructed` dict passed to `compose_root(config, pre_constructed=...)` (AZ-618 umbrella → AZ-620 c6 storage phase + AZ-623 c7 inference phase). All seven backbones (`ultra_vpr`, `net_vlad`, `mega_loc`, `mix_vpr`, `sela_vpr`, `eigen_places`, `salad`) have wired strategy modules + `_preprocessor_*` siblings + `_faiss_bridge`; their `BUILD_VPR_<variant>` env flags default OFF (tests/CI must opt in per strategy — see `runtime_root/vpr_factory.py::_is_build_flag_on`). The cycle-1 `C2VprConfig.strategy` default is `net_vlad` (the mandatory simple-baseline per Plan-phase D-C2-1) — `ultra_vpr` remains the Documentary Lead's PRIMARY backbone but additionally requires a pre-compiled `.trt` engine produced by C10's engine compiler (AZ-321). The `c2_vpr` slot lists `("c6_descriptor_index", "c7_inference")` in `AIRBORNE_REQUIRED_PRE_CONSTRUCTED_KEYS`; missing keys raise `AirborneBootstrapError` at composition time, not at first frame.
**Upstream dependencies**:
- Camera ingest thread → `NavCameraFrame` (parallel fan-out with C1; same frame, distinct queue depth).
- C7 InferenceRuntime → backbone forward pass (TRT/ONNX/PyTorch per active runtime).
@@ -92,6 +94,7 @@ C2 is read-only against C6 during F3/F4/F6. Pre-flight, F1 triggers C10 (after C
| PyTorch | matches simple-baseline track | FP16 baseline (NetVLAD / MixVPR mandatory) |
| UltraVPR (research code drop) | upstream HEAD pinned per Plan-phase | Documentary Lead PRIMARY backbone |
| MegaLoc, MixVPR, SelaVPR, EigenPlaces, NetVLAD | upstream HEAD pinned per Plan-phase | Secondary + mandatory simple-baselines |
| OpenCV (`cv2`) | `>=4.11.0.86,<4.12` (cycle-1 relaxed pin; D-CROSS-CVE-1 deferred — see `_docs/_process_leftovers/2026-05-11_d_cross_cve_1_opencv_pin_deferred.md`) | Image decode + colour-space conversions in the per-strategy `_preprocessor_*.py` modules |
**Error Handling Strategy**:
- `VprBackboneError`: backbone forward pass failed (CUDA OOM, TRT engine deserialize mismatch). C2 emits no `VprResult`; C5 falls back to VIO-only with provenance label `visual_propagated` (AC-1.4).